Search - frequency divider

[VHDL-FPGA-Verilog] frequency-divider

Description: 基于VHDL语言实现的数控分频器的设计及其仿真-Based on the numerical control language realization VHDL prescaler design and its simulation
Platform: | Size: 93184 | Author: 刘海 | Hits:

[VHDL-FPGA-Verilog] clk_div

Description: 介绍了一种基于FPGA的小数分频器的分频原理及电路设计- decimal frequency divider based on FPGA
Platform: | Size: 183296 | Author: hnzkhy | Hits:

Description: 该项目用D触发器设计了一个基于VHDL的16分频的分频器，其中包括仿真时序图。-Of the project design with D flip-flop frequency divider 16 points based on VHDL, including simulation timing diagram.
Platform: | Size: 147456 | Author: longdonghuo | Hits:

[VHDL-FPGA-Verilog] div16_tff

Description: 该工程设计了一个16分频的分频器，电路采用T触发器，已通过仿真。-The engineering design of a 16 frequency divider circuit using T flip-flop, through simulation.
Platform: | Size: 144384 | Author: longdonghuo | Hits:

[VHDL-FPGA-Verilog] fsk_tz

Description: vhdl实现FSK调制，本次毕业设计的数据速率 1.2kb/s，要求产生一个1.2kHz的正弦信号，对正弦信号每周期取100个采样点，因此要求产生3个时钟信号：1.2kHz（数据速率）、120kHz（产生1.2kHz正弦信号的输入时钟）、240kHz（产生2.4kHz正弦信号的输入时钟）。基准时钟已由一个外部时钟120MHz提供，要得到前面三种时钟，就需要首先设计一个模50的分频器产生240kHz信号，再设计一个二分频器，生产一个120kHz的信号，然后再前面的基础上再设计一个模100的分频器，用来产生1.2kHz的随机信号产生速率。-vhdl achieve FSK modulation, the graduate design data rate of 1.2kb/s to produce a sinusoidal signal of 1.2kHz, take the 100 sampling points per cycle of the sinusoidal signal, thus requiring to produce the three clock signals: 1.2 kHz (data rate , 120kHz, a 1.2kHz sine input clock signal), 240kHz (a 2.4kHz sine signal input clock). 120MHz reference clock has been an external clock to get the first three clock, you need to first design a mold 50 of the divider to produce a 240kHz signal, re-design of a two frequency divider to produce a 120kHz signal, and then the front of the base on the re-design of a mold 100 of the divider used to generate the 1.2kHz random signal generator rate.
Platform: | Size: 1024 | Author: 杨 | Hits:

[VHDL-FPGA-Verilog] fenpin

Description: VHDL编写的分频器，占空比为1:1，可以根据需要，修改计数器，完成不同频率的分频-Divider in VHDL, the duty cycle of 1:1, as needed, modify the counter, complete different frequency divider
Platform: | Size: 1024 | Author: 小幂控 | Hits:

[Other] dcm25test

Description: 采用建立IP核的办法，DCM实现25M分频-The establishment of IP nuclear approach, DCM 25M frequency divider
Platform: | Size: 959488 | Author: 陆河辉 | Hits:

[VHDL-FPGA-Verilog] 5fenpinqi

Description: 实现5分频的分频器程序，并且使用仿真文件进行测试通过。-5 frequency divider program, and tested through simulation file.
Platform: | Size: 2048 | Author: 杨鹏飞 | Hits:

[Other] op_div_5

Description: VHDL写的奇数次分频电路，占空比为50 .-VHDL to write odd frequency divider circuit, the duty cycle is 50 .
Platform: | Size: 1024 | Author: 齐飞 | Hits:

[VHDL-FPGA-Verilog] div

Description: Quartus下VHDL语言编写的常用分频器（2、4、5、8、10、50、100）等，包含模块图。-Frequency divider in common use under Quartus environment,with module block
Platform: | Size: 9216 | Author: 陈国庆 | Hits:

[VHDL-FPGA-Verilog] odd_division

Description: 实现了时钟奇数（11）分频器，其它奇数分频只要重新计算div1和div2参数就行了。-Realize the clock odd (11) frequency divider, other odd frequency division as long as recount div1 and div2 parameters will do.
Platform: | Size: 30720 | Author: 张明涛 | Hits:

[VHDL-FPGA-Verilog] int_div

Description: 任意计数的分频器，实现功能超强；只需改变分频数字而已-frequency divider vhdl
Platform: | Size: 1024 | Author: gongwenbiao | Hits:

[Com Port] 8253

Description: 微机实验 1、编写程序：使用8253的计数器0和计数器1实现对输入时钟频率的两级分频，得到一个周期为1秒的方波，用此方波控制蜂鸣器，发出报警信号，也可以将输入脚接到逻辑笔上来检验程序是否正确。 2、使用8253，编写一个时钟程序。 -Microcomputer Experiment 1, the preparation process: 8253 counter 0 and counter two of the input clock frequency divider, a period of 1 second square wave, the square wave control buzzer alarm signal, but also logic input pin to pen up the inspection program is correct. 2, 8253, to write a clock program.
Platform: | Size: 64512 | Author: 庄剑文 | Hits:

[STL] cshiyan2012

Description: 基于EDA软件平台上，用硬件描述语言verilog设计完成分频器、计数器、串行移位输出器、伪码发生器、QPSK I/Q调制器、QPSK I/Q解调器，基于选项法中频调制器，再将各个模块综合起来组成一个完整系统；并用quartusII软件对其进行仿真验证。-EDA software platform based on the hardware description language verilog design complete shift of the frequency divider, timer, serial output, pseudo-code generator, the QPSK the I/Q modulator, QPSK I/Q demodulator based option law IF modulator, and then the individual modules together to form a complete system simulation and its quartusII software.
Platform: | Size: 1905664 | Author: 赵旋 | Hits:

[VHDL-FPGA-Verilog] clkdiv

Description: 任意分频电路的verilog实现，包含奇分频和偶分频-Arbitrary divider circuit verilog achieve, contains odd and even frequency divider
Platform: | Size: 32768 | Author: sun | Hits:

[VHDL-FPGA-Verilog] Frequency_Div

Description: it is vhdl code for "frequency divider" which was implemented and run in altera quarts- -it is vhdl code for "frequency divider" which was implemented and run in altera quarts- II
Platform: | Size: 24576 | Author: Henal patel | Hits:

[Other] 1freqdiv

Description: 使用VHDL代码高速而有效的实现了频率的分频，整个工程全部上传，bit文件可以直接下载-VHDL code fast and effective frequency divider, the whole project upload all bit file can be downloaded directly
Platform: | Size: 2048 | Author: kindheart | Hits:

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